1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a selection gate transistor in a memory cell portion which is, for example, applied to a NAND type flash memory.
2. Description of the Related Art
FIG. 57 shows a sectional view of memory cell transistors and selection gate transistors taken in a gate length “L” direction in a conventional NAND type semiconductor memory device.
A contact hole 34 is formed between the gate electrodes of the selection gate transistors in self-alignment with respect to these gate electrodes. A TEOS film 29 is deposited on the gate sidewalls of the memory cell transistors to improve hot carrier characteristics.
On the other hand, the selection gate transistors are arranged such that the TEOS film 29 of the gate sidewalls thereof is removed before the contact hole 34 is opened to prevent the short-circuit between a contact filling material and the gate electrodes because the TEOS film 29 is etched when the contact hole 34 is opened. Since an impurity is simultaneously ion-implanted in the channel regions and source/drain diffusion layer regions 28 of the memory cell transistors and the selection gate transistors, the impurity distribution in the channel regions and the source/drain diffusion layer regions 28 is similar in the memory cell transistors and the selection gate transistors.
In the NAND type semiconductor memory device, when data “1” is written to a memory cell (i.e. when electrons are not implanted in floating gates and a threshold value in erasing is maintained), the electrons are prevented from being implanted in the floating gates 5 and 11 by charging an initial potential from a bit line through the selection gate transistor connected to the memory cell transistor, applying a writing voltage to a selected word line and applying a transfer voltage to non-selected word lines, and increasing the potential of the channel region of the memory cell transistor making use of capacitance coupling. As a result, the capacitance of the channel region is reduced by decreasing the concentration of the impurity therein so that the potential of the channel region is liable to increase, which improves data “1” writing characteristics.
However, there are such circumstances that the non-volatile semiconductor memory device cannot be normally operated by a decrease in the threshold voltage of the selection gate transistors and an increase in the off-leak current thereof which are caused when the concentration of the impurity in the channel regions is reduced. This is because that the distribution of the impurity in the channel regions of the memory cell transistors is the same as that of the impurity in the channel regions of the selection gate transistors.
FIG. 58 shows a sectional view of a part of manufacturing processes of a memory cell and a selection gate transistor of a conventional NAND type flash memory taken along the gate length direction thereof.
In the figure, reference numeral 1 denotes a silicon substrate and reference numeral 3 denotes a well/channel region. The memory cell and selection gate transistor are simultaneously subjected to impurity ion implantation into the well/channel region 3 and formation of a gate insulation film 4.
The memory cell of the NAND memory cell unit has a gate structure where a charge accumulation layer (floating gate) and a control gate layer are stacked one atop the other via an ONO film 13 on a substrate. The floating gate comprises a first layer of polysilicon 5 and a second layer as a floating gate 11 which are deposited in layers. The control gate layer 14 is formed of a polysilicon/WSi laminated film. Here, indicated by reference numeral 15 is a silicon nitride film and 20 is a silicon oxide film. Gate electrodes of the selection gate transistor are designated by reference numerals 5 and 11. Reference numeral 28 denotes a source/drain diffusion layer of the memory cell and selection gate transistor. A contact hole is to be formed between the gate electrodes of the selection gate transistor.
Impurity ion implantation for forming the source/drain diffusion layer 28 of the memory cell and selection gate transistor is carried out simultaneously, and the source/drain diffusion layer 28 of the selection gate transistor is connected to the memory cell unit at one end and is electrically connected to a bit line or source line through the contact hole at the other end.
FIG. 59 shows a concentration distribution of a p-type impurity in a substrate depth direction at a channel region of the selection gate transistor along the line C-C′ shown in FIG. 58 and a concentration distribution of a p-type impurity in the substrate depth direction at a channel region of the memory cell along the line D-D′ shown in FIG. 58.
As mentioned above, since an impurity is implanted simultaneously into the channel regions of the memory cell and selection gate transistor, the impurity distributions of the both channel regions become the same as shown in FIG. 59.
It is known that a NAND type flash memory is adapted to prevent the data of an unselected block being read out at a time of data reading by turning off the selection gate transistor. For this purpose, in order to allow a threshold voltage of the selection gate transistor to satisfy the limitations of the cut-off characteristics, it is necessary to control the impurity concentrations in the channel regions.
The NAND type flash memory, on the other hand, is adapted to prevent electrons to be introduced into the floating gates 5 and 11 when “1” data is written to the memory cell (i.e. when a threshold value during an erased state is maintained without implanting electrons into the floating gate), by charging the memory cell to the initial potential through the bit line via the selection gate transistor connected to the memory cell, applying a write voltage and a transfer voltage to a selected word line and an unselected word line, respectively, and rising the potential of the channel region of the memory cell by means of capacitive coupling. Thus, decreasing each impurity concentrations of the respective channel regions reduces the channel capacity, which facilitates a rise in potential in the channel region and improves the “1” data writing efficiency.
Conventionally, however, since the impurity distributions of the channel regions of the memory cell and selection gate transistor are the same as stated above, when decreasing the impurity distribution in the channel regions in order to improve the “1” data writing efficiency as mentioned before, a trade-off relationship arises in which the threshold voltage of the selection gate transistor decreases and an off-leak current increases.